1. Field of the Invention
The invention relates to examples of a memory cell incorporating a buffer circuit, and a random access memory comprising such a memory cell.
It relates to the field of circuit design, more particularly using CMOS technology.
It finds applications, in particular, in electronic components, for example integrated-circuit memory circuits (so-called xe2x80x9cstand alonexe2x80x9d circuits) of SRAM type (Static Random Access Memory) or DRAM type (Dynamic Random Access Memory), microcontrollers, application specific integrated circuits, etc.
2. Description of the Related Art
In the prior art, it is known practice to make a memory cell comprising on the one hand a buffer circuit whose output is linked to the input so as to form a logic latch, and on the other hand read- and/or write-access transistors for carrying out a read and/or write operation in the memory cell. In conventional manner, a buffer circuit comprises two cascaded inverters.
Represented diagrammatically in FIG. 1 is a CMOS technology inverter. The inverter 1 comprises an N type MOS transistor referenced MN11 and a P type MOS transistor referenced MP11, which are disposed in series between a first terminal 11 and a second terminal 12. The terminal 11 is brought to a potential Vdd, and the terminal 12 is brought to a potential Gnd which is less than the potential Vdd. In general, the potential Vdd is a positive supply potential, and the potential Gnd is a negative supply potential or a ground potential. The drains of the transistors MN11 and MP11 are linked together and form the output OUT of the inverter 1. Likewise, the control gates of the transistors MN11 and MP11 are linked together and form the input IN of the inverter 1. Finally, the source of the transistor MP11 is linked to the terminal 11 and the source of the transistor MN11 is linked to the terminal 12. The manner of operation of this inverter is well known to the person skilled in the art and does not call for any particular comments.
Represented diagrammatically in FIG. 2 is a first memory cell known in the prior art. The memory cell 20 comprises a first inverter 2 and a second inverter 3. These are MOS technology inverters such as the one described above with regard to the diagram of FIG. 1. The output of the inverter 2 is linked to the input of the inverter 3 so as to form a buffer circuit. Furthermore, the output of the inverter 3 is linked to the input of the inverter 2 so as to form a logic latch. Furthermore, the cell 20 comprises a first access transistor M2 and a second access transistor M3. These are for example N type MOS transistors. The transistor M2 is disposed between the output of the inverter 2 and a node which is linked to a bit line BL1 of the memory incorporating the memory cell 20. Likewise, the transistor M3 is disposed between the output of the inverter 3 and a node which is linked to a bit line BL2 of the memory incorporating the cell 20. The bit lines BL1 and BL2 are said to be dual, insofar as, during operation, they are brought to mutually symmetric potentials, corresponding to mutually inverse logic levels. The control gates of the access transistors M2 and M3 are linked to a word line WL of the memory incorporating the cell 20. As may be seen, the memory cell 20 of FIG. 2 comprised at least 6 MOS transistors.
In order to reduce the silicon area occupied by a memory cell on a doped silicon substrate, attempts have already been made to reduce the number of MOS transistors comprises in the memory cell.
FIG. 3, in which the same elements as in FIG. 2 bear the same references, shows diagrammatically a second memory cell 30 according to the prior art, which has already been proposed for this purpose. The cell 30 is distinguished from the cell 20 described above with regard to FIG. 2, in that it comprises only four MOS transistors. Specifically, the respective transistors MP11 of the inverter 2 and of the inverter 3 are replaced by respective resistors R1. Since these resistors occupy less silicon area than the P type MOS transistors for which they are substituted, the sought-after reduction of area occupied by the memory cell is obtained.
However, the making of the resistors R1 requires the implementation of a particular process which makes fabrication more complex.
This is why a memory cell of the type of that represented in FIG. 4 has also been proposed. This memory cell 40, known in the prior art, corresponds substantially to the memory cell 30 described above with regard to FIG. 3. It is distinguished therefrom in that the respective resistors R1 of the inverters 2 and 3 are replaced by short-circuits. In reality, the role played by the resistors R1 of the cell 30 of FIG. 3 is played, in the cell 40, by the leakage resistors of the access transistors M2 and M3. For this purpose, the latter are preferably P type MOS transistors with a low threshold voltage, whose leakage resistances are high. Moreover, the respective transistors MN11 of the inverters 2 and 3 are preferably transistors having a high threshold voltage. The cell 40 comprises just four MOS transistors and does not exhibit the aforementioned drawbacks of the memory cell 30 of FIG. 3.
The operation of the memory cell 40 is however difficult to control on account of the difficulty in controlling the leakage currents of the transistors M2 and M3. In particular, the operation of the memory cell 40 is somewhat unreliable for low values of the supply voltage (this voltage being the difference between the potentials Vdd and Gnd).
There is known from U.S. Pat. No. 5,907,502 a buffer circuit comprising an N type MOS transistor and a P type MOS transistor, which are disposed in series between a first terminal brought to a first given potential and a second terminal brought to a second given potential. The second potential is less than the first potential. The sources of the transistors are linked together and form the output of the buffer circuit. The control gates of the transistors are linked together and form the input of the buffer circuit. The drain of the N type MOS transistor is linked to said first terminal and the drain of the P type MOS transistor is linked to said second terminal.
This buffer circuit therefore comprises just two MOS transistors but it may advantageously be substituted for a buffer circuit of known type comprising two CMOS technology inverters in cascade such as in the memory cell 20 described above with regard to the diagram of FIG. 2, which comprises four MOS transistors.
An embodiment of the invention is a memory cell comprising such a buffer circuit, thus occupying a small silicon area.
Embodiments of the invention relate to examples of a memory cell comprising a buffer circuit such as defined above, whose output is linked to the input so as to form a logic latch.
In a first embodiment, a write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between a first node linked to a bit line and a second node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.
Another embodiment of the invention relates to a random access memory comprising at least one memory cell of the aforementioned type. This is in particular an SRAM type static memory, although the invention is in no way limited to this example.
An embodiment of the invention provides a write- and read-access transistor disposed between a primary node linked to a bit line and the input of the buffer circuit. A control gate of the write- and read-access transistor is linked to a secondary node on a read and write word line. A read-protection transistor is disposed between the input and the output of the buffer circuit, and a control gate of the read-protection transistor is linked to a node on a read word line.
Further embodiments of the invention provide methods of operation of the memory cells.